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01 · Storage
02 · Systems
03 · Facilities
04 · Quantum
05 · Processing
06 · Interconnects
07 · Memory
08 · TCO
Memory
Technologies
Memory bandwidth — not raw compute FLOPS — is the binding bottleneck in modern AI. Transformer attention is memory-bandwidth-bound. LLM inference throughput scales with HBM bandwidth. The race to widen the memory wall has made High Bandwidth Memory the most strategically contested component in AI hardware, with three supply chain actors — SK Hynix, Samsung, and Micron — determining GPU availability and price across the entire industry.
◆ The Memory Wall
GPU FLOPS Scale 2×/yrMemory BW Scales 1.4×/yrDivergence Reshapes AI Architecture
AI Memory Market 2026
$38.6B
+34.2% YoY · HBM + Server DRAM + CXL
HBM3E Bandwidth / Stack
1.2TB/s
+50% vs. HBM3 · 24–36 GB capacity
B200 Total HBM Bandwidth
8.0TB/s
192 GB HBM3E · 8 stacks · 2.4× H100
SK Hynix HBM Share
53%
Samsung 33% · Micron 14% · 2026
HBM Bandwidth per Stack by Generation — GB/s
Server Memory Revenue by Type · 2026
+40%
HBM supply capacity added by end-2026 — SK Hynix Icheon expansion, Samsung Taylor TX, Micron Boise HBM4 investment
$0.8B→$12B
CXL memory market 2026→2031 — CXL 3.0 enables memory pooling across hosts, cutting stranded memory waste from ~40% to <10%
2.35×
Samsung HBM-PIM performance-per-watt gain on BERT inference vs. standard HBM3 — SK Hynix AiM delivers 1 TFLOPS effective in-memory
The Bandwidth-Compute Divergence: A 70B parameter FP16 model requires moving ~140 GB of weights per generated token. At 8 TB/s (B200), that yields only ~57 tokens/second at theoretical peak — before KV-cache, batching overhead, or memory fragmentation. Even NVIDIA's best GPU spends a large fraction of inference time waiting for memory, not computing. Memory capacity, bandwidth, and latency remain the defining constraints of every AI workload in 2026 — not FLOPS.
01 · Storage
02 · Systems
03 · Facilities
04 · Quantum
05 · Processing
06 · Interconnects
07 · Memory
08 · TCO
HBM Generation Roadmap · 2013–2027E
Gen Year BW / Stack Capacity Key GPU Status
HBM4 2026–27 >2.0 TB/s 48–64 GB Rubin, CDNA4 Sampling
HBM3E 2024–26 1.2 TB/s 24–36 GB B200, MI325X Production
HBM3 2023–25 819 GB/s 24 GB H100, MI300X Deployed
HBM2E 2020–23 460 GB/s 16 GB A100 80G Legacy
HBM2 2016–20 307 GB/s 8 GB V100, Vega EOL
HBM1 2013–16 128 GB/s 1–4 GB AMD Fury EOL
Memory Hierarchy — 2026 Reference
Tier Bandwidth Latency $/GB Capacity
HBM3E (On-Die) 8.0 TB/s ~1 ns $8–12 192 GB
GDDR7 (Discrete) ~1.8 TB/s ~3 ns $2–4 24–48 GB
DDR5 (CPU-Local) ~460 GB/s ~70 ns $0.08 2–12 TB
CXL-DRAM (Pooled) ~280 GB/s ~150 ns $0.10 4–64 TB
NVMe SSD (Local) ~14 GB/s ~100 µs $0.08 8–128 TB
Object Storage ~1–10 GB/s ~10 ms $0.02 Unlimited
HBM TSV stacking lead time: 6–8 months
SK Hynix process lead: 12–18 months
512 GB RDIMM: production mid-2026
LPDDR5X: 8,533 MT/s · <0.9V
The Memory Wall — FLOPS vs. Bandwidth Growth (V100 = 1.0)
AI Memory Forecast by Segment — $B · 2026–2031F
▲ Bull Case
$148B
30.8% CAGR · 2026–2031
HBM4 supercycle — AGI-scale clusters require 384+ GB/GPU; CXL 3.0 inflects by 2027; PIM reaches 15% of HBM shipments; average HBM capacity per GPU doubles
● Base Case
$112B
23.8% CAGR · 2026–2031
HBM4 ramps on schedule; DDR5 completes server transition by 2027; CXL reaches meaningful volumes from 2028; three-vendor HBM competition normalizes pricing
▼ Bear Case
$74B
13.9% CAGR · 2026–2031
Model compression (INT4/INT2, MoE sparsity) cuts HBM capacity demand; AI investment cycle cools post-2027; CXL delayed by software ecosystem immaturity
Engage the Full Intelligence Report
The complete Memory Technologies module delivers 65+ pages of HBM supply chain analysis, vendor competitive intelligence, CXL architecture deep-dives, PIM roadmaps, and LLM memory footprint modeling for every major AI workload class.
HBM Supply Chain Tracker
Vendor Capacity Models
CXL Architecture Deep-Dive
LLM Memory Footprint Data
PIM Competitive Matrix
DDR5 / LPDDR5X Market Forecast
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